Merging multiplexers to reduce ROM area

ABSTRACT

Systems and method for reducing the die area occupied by a programmable logic device are provided. The systems and methods relate to a programmable logic device comprising a plurality of multiplexers. A portion of the multiplexers form a multiplexer cone. The cone is characterized in that all but one of the multiplexers in the cone has an output which only feeds data inputs of other multiplexers in the cone. Methods according to the invention preferably include identifying two multiplexers in the cone. The two multiplexers are selected based on the fact that the two multiplexers receive substantially identical data inputs and are not used by the programmable logic device to provide outputs during a single clock cycle. Finally, systems and methods according to the invention merge the functions of the two multiplexers into a single merged multiplexer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under Title 35, United States Code,§ 119(e), of U.S. Provisional Application No. 60/685,226 filed May 27,2005.

BACKGROUND OF THE INVENTION

This invention relates to ROMs (Read-Only Memories). More specifically,this invention relates to the use of multiplexers within ROMs.

ROMs typically use multiplexers for implementing the required ROMfunctions such as basic reading, writing and addressing functions. Themultiplexers that are used in ROMs are usually very large binarymultiplexers. The very large binary multiplexers are relativelyexpensive in die area—i.e., they occupy relatively large areas of spaceon a typical die used in the implementation of semiconductor circuitryof the type used for programmable logic devices (PLDs).

The description herein relates directly to PLDs. Nevertheless, the scopeof the description herein should not be considered to be limited toPLDs. Rather, the scope of the descriptions herein extends to anycircuitry in which multiplexers are implemented.

FIG. 1 shows an example of a prior art ROM implementation 100. ROM 102includes 8 addresses 102 of the Read-Only Data that provides 4-bit widedata. The 4-bit wide data is implemented as four 8:1 binary multiplexers104. Address lines 106 may be used as control lines to dictate theoutput of multiplexer 104.

In order to implement ROMs using such conventional multiplexerarrangements, commonly-known synthesis tools convert each multiplexerinto separate Look-up Tables (LUTs). The following table shows therelative area (as expressed in terms of the estimated number of LUTsthat are required to implement the prior art ROM) used by such ROMs.

Number of Area Estimate in Data Width Data Words 4-input LUTs  8 bits 3224 16 bits 32 60 16 bits 64 111 32 bits 128 447It can be seen from the foregoing table that the relative area costdepends on the size and type of ROM being implemented. The areaestimates were calculated by synthesizing ROMs of the described sizesfilled with randomly-generated data. Synthesis was performed using aproprietary software package of Altera Corporation of San Jose, Calif.

In view of the significant area cost associated with ROMs that use largemultiplexers, it would be desirable to provide alternative synthesissystems and methods for implementing ROMs that use less multiplexersthan conventional ROMs.

It would also be desirable to re-use multiplexers under certainconditions and in certain implementations of ROMs instead of convertingeach multiplexer into Look-up Tables separately.

SUMMARY OF THE INVENTION

It is an object of the invention to provide alternative synthesissystems and methods for implementing ROMs that use fewer multiplexersthan conventional ROMs.

It is a further object of the invention to re-use multiplexers undercertain conditions and in certain implementations of ROMs.

A method for reducing the die area occupied by an electronic circuitcomprising a plurality of multiplexers is provided. In one embodiment ofthe invention, the method includes identifying two multiplexers in adesign of the electronic circuit from the plurality of multiplexers. Thetwo multiplexers preferably receive identical data inputs and are notused by the electronic circuit to provide outputs during the same clockcycle. Furthermore, the method includes modifying the design of theelectronic circuit to merge the two multiplexers into a mergedmultiplexer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the invention will be more apparentupon consideration of the following detailed description, taken inconjunction with the accompanying drawings, in which like referencecharacters refer to like parts throughout, and in which:

FIG. 1 shows a schematic diagram of a prior art group of multiplexersfor use in a ROM or portions thereof;

FIG. 2 shows a schematic diagram of a combination of multiplexers uponwhich systems and methods according to the invention can be implemented;

FIG. 3 shows a schematic diagram of the multiplexer circuitryimplemented according to the invention;

FIGS. 4A-C show schematic diagrams of examples of multiplexer conesaccording to the invention;

FIGS. 5A-B show a set of schematic diagrams which illustrate a firstsystem and method of generating new control logic according to theinvention; and

FIG. 6 is a simplified block diagram of an illustrative system employingcircuitry in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

The basic concept underlying the invention is that, under certainconditions, the functions, and consequently, the die area for twoseparate multiplexers can be combined into a single multiplexer, therebysaving die area.

The following two conditions should preferably be met in order tocombine two multiplexers in systems and methods according to theinvention. Each of the multiplexers should preferably not be configuredto be used substantially simultaneously—i.e., in same clock cycle.Second, each of the multiplexers should have the same data inputs butdifferent control inputs. Under these constraints, two multiplexers canbe replaced by a single multiplexer.

In ROM circuitry according to the invention, a single multiplexerreplaces two multiplexers as follows: The new multiplexer is connectedin place of both multiplexers. This is possible because bothmultiplexers use the same data inputs.

The control lines for each of the individual multiplexers may bedifferent. Therefore, the control lines for each of the originalmultiplexers should preferably be accessible by the merged multiplexeraccording to the invention. When the functions associated with the firstmultiplexer are selected the control lines of the new multiplexer arefed by the set of control lines originally associated with the firstmultiplexer. When the functions associated with the second multiplexerare selected the control lines are preferably fed by the set of controllines originally associated with the second multiplexer.

This technique can preferably be applied to any kind of multiplexer.However, the largest area savings usually result from applying thetechnique to ROMs. One reason that ROMs are well-suited to takeadvantage of the benefits provided by the invention is that designs forROMs frequently reuse the same Read-Only Data in different modules.Furthermore, a single ROM can use many hundreds of multiplexer-basedLUTs. For at least the two preceding reasons ROMs can obtain particularadvantage from the benefits according to the invention.

In order to identify which multiplexers in a particular design may bemerged using techniques according to the invention, the following stepsmay be followed. First, it is possible to divide all multiplexers in adesign into groups called multiplexer cones. The term multiplexer conesis defined herein to be a group of connected multiplexers, the outputsof all but one of which only feed data inputs of other multiplexers inthe group. If two multiplexers which are part of the same multiplexercone have individual data inputs, and have outputs that cannot be usedsimultaneously, then they satisfy the conditions required to be merged.

Multiplexers may be grouped into multiplexer cones using the followingexemplary algorithm, according to the invention:

for all nodes, N, in the design do if N is a mux and N is not a memberof any cone then C = create a new empty cone expand_cone(N, C) end ifend for function expand_cone(N, C) insert node N into cone C for allnodes, I, feeding data inputs of N if I is a mux and all outputs of Ifeed muxes in C then expand_cone(T, C) end if end for end functionThen, two (or more) multiplexers (preferably in the same cone) arereplaced by a new, single multiplexer. The data inputs of the newmultiplexer are preferably identical to the data inputs of the originalmultiplexer.

The next step in the technique is calculating the control lines of thenew multiplexer. The new multiplexer preferably performs an identicalfunction to either of the original multiplexers. However, as statedabove, the original multiplexers have different control lines andperform, therefore, different logic functions. This contradiction canpreferably only be resolved because each of the original multiplexerswas never used at the same time as the other original multiplexer. Thus,at any given time, the new multiplexer uses whichever set of controllines correspond to the original multiplexer which would have been usedat that time—i.e., during that clock cycle.

In order to generate new control logic according to the invention, acopy of the multiplexer cone is preferable created. The copy preferablyreplaces the original multiplexers and their control lines with a singlemultiplexer having additional logic which implements the control linesas needed. Any other primary data input—i.e., an input not used toreplicate the original control logic—to the replicated cone is treatedas a “don't care” value.

Furthermore, known optimization techniques may be used to collapsemultiplexers fed by “don't care” inputs. In this way the additionallogic required to coordinate the control logic can also be substantiallyreduced.

In summation, the algorithm according to the invention preferably is:

find all multiplexer cones for each cone do loop try to find a pair ofmultiplexers in the cone with identical data if found a pair thenreplace the pair with a single multiplexer end if where found a pair endfor

It has been shown that certain systems and methods according to theinvention obtain some advantages over the prior art. For example, thesystems and methods according to the invention reduce required siliconarea by reducing the number of large ROMs or multiplexers required toimplement the design. Less silicon area is also required because theinvention yields a large reduction in required logic elements. Finally,the additional logic required for the new control logic is typicallyjust a few 2:1 multiplexers as shown in more detail in FIG. 5B anddescribed in the text corresponding thereto.

It should be noted that in simulations performed in Altera Corporation'sbenchmark design sets, area reductions of up to 30% were obtained.

Heretofore, the basic principles of the invention have been set forth.FIGS. 2-6, and the associated written descriptions, show particularportions of the technique according to the invention.

FIG. 2 shows a schematic diagram of a combination of multiplexers 202and 204 upon which systems and methods according to the invention can beimplemented. Data inputs 206 are identical for both multiplexer 202 and204. Control lines 208 and 210, however, are different for each ofmultiplexers 202 and 204. Multiplexers 212 and 214 are used to selectthe appropriate output from the multiplexers 202 and 204. Multiplexers212 and 214 are typically controlled by conditional operators, or othersuitable operators, C₀ and C₁, which respond to signals from otherportions of the circuit and, in response, select which output isappropriate. At times, for example, C₁ might select output R from input216 to be selected in response to some preferably predetermined circuitcondition.

FIG. 3 shows a schematic diagram of multiplexer circuitry according tothe invention. One difference between the multiplexer circuitry shown inFIG. 3 and the multiplexers shown in FIG. 2 is that the two multiplexers202 and 204 have been replaced by a single multiplexer 302. Anotherdifference is that the two control lines 308 and 310 have beenmultiplexed using multiplexer 318. The output of multiplexer 318provides the appropriate control signal for multiplexer 302 in responseto the signal from conditional operator C₀. Preferably, the controllines of multiplexer 302 are fed by A₁ whenever multiplexer 202 wouldhave been selected and by A₂ whenever multiplexer 204 would have beenselected.

FIGS. 4A-C show examples of multiplexers that form multiplexer conesaccording to the invention. As defined above multiplexer conespreferably include a group of connected multiplexers. The outputs ofpreferably all but one of which only feed data inputs of othermultiplexers in the group.

FIG. 4A shows one group where each of the multiplexers are two-inputmultiplexers 402, 404 and 406. Multiplexer 402 is the only multiplexerwhich has an output that does not feed an input of other multiplexers inthe group. Preferably, any of the multiplexers could be merged with oneanother because they are all two-input multiplexers (when the other twoconditions enumerated above are satisfied—i.e., they have the sameinputs and they do not provide outputs in the same clock cycle).

FIG. 4B shows a multiplexer cone including multiplexers 412, 414, 416,and 418. At least multiplexers 414 and 418 as well as 412 and 416 can becombined, respectively (assuming, again, that the two conditions aremet).

Finally, FIG. 4C shows a multiplexer cone which is similar to the coneshown in FIG. 4A. The only difference is the addition of multiplexer 428to the other three multiplexers.

FIG. 5A and FIG. 5B illustrate the technique according to the inventionof generating new control logic. It can be seen that all the elementsshown in FIGS. 5A and 5B are essentially the same as elements shown inFIG. 3 with the exception of elements 516 in FIGS. 5A and 5B andelements 522, 524 and 526 in FIG. 5B. Multiplexer 516 is additionallogic which is fed by a control line from a suitable conditionaloperator from the rest of the circuitry. Multiplexers 522, 524 and 526each provide logic for the appropriate control logic to mergedmultiplexer 502. It should be noted that Xs symbolize “don't care”logic. It should also be noted that multiplexers 522, 524 and 526 may bemerged according to known optimization techniques to collapsemultiplexers fed by “don't cares” to form a control circuit that isshown as multiplexer 318 in FIG. 3.

Thus, a technique for merging multiplexer-based ROMs and othermultiplexer-based circuitry has been provided.

FIG. 6 illustrates a PLD or other circuitry in a data processing system600 that may incorporate a merged multiplexer in accordance with theinvention. Data processing system 600 may include one or more of thefollowing components: a processor 604; memory 606; I/O circuitry 608;and peripheral devices 610. These components are coupled together by asystem bus or other interconnections 620 and are populated on a circuitboard 630 (e.g., a printed circuit board), which is contained in anend-user system 640. Any of the interconnections between element 650 andany other elements may be made in a manner known to one skilled in theart.

System 600 can be used in a wide variety of applications, such ascomputer networking, data networking, instrumentation, video processing,digital signal processing, or any other application where the advantageof using programmable or reprogrammable logic is desirable. Circuitry650 can be used to perform a variety of different logic functions. Forexample, circuitry 650 can be configured as a processor or controllerthat works in cooperation with processor 604. Circuitry 650 may also beused as an arbiter for arbitrating access to a shared resource in system600. In yet another example, circuitry 650 can be configured as aninterface between processor 604 and one of the other components insystem 600. It should be noted that system 600 is only exemplary, andthat the true scope and spirit of the invention should be indicated bythe following claims.

It will be understood, therefore, that the foregoing is onlyillustrative of the principles of the invention, and that variousmodifications can be made by those skilled in the art without departingfrom the scope and spirit of the invention, and the present invention islimited only by the claims that follow.

What is claimed is:
 1. A method for reducing the die area occupied by anelectronic circuit comprising a plurality of multiplexers, the methodcomprising: identifying, in a design of the electronic circuit, twomultiplexers from the plurality of multiplexers, wherein the twomultiplexers receive identical data inputs and are not both used by theelectronic circuit to provide outputs during any single clock cycle, andwherein each respective one of the two multiplexers is fed by arespective control line; modifying the design of the electronic circuitto merge the two multiplexers into a merged multiplexer; feeding each ofthe respective control lines of the two multiplexers into data inputs ofa control multiplexer; and using output of the control multiplexer as acontrol line for the merged multiplexer.
 2. The method of claim 1further comprising: identifying a plurality of multiplexers that form amultiplexer cone; wherein: the identifying the two multiplexerscomprises identifying the two multiplexers from among the plurality ofmultiplexers that form the multiplexer cone.
 3. The method of claim 2,wherein the multiplexer cone is characterized as a plurality ofmultiplexers the outputs of all but one of which only feed data inputsof other multiplexers in the cone.
 4. A method for reducing the die areaoccupied by a programmable logic device, the device comprising aplurality of multiplexers, a portion of the multiplexers forming amultiplexer cone, all but one of the multiplexers in the cone havingoutputs which only feed data inputs of other multiplexers in the cone,the method comprising: identifying two multiplexers in the cone, whereinthe two multiplexers receive substantially identical data inputs and arenot both used by the electronic circuit to provide outputs during anysingle clock cycle, and wherein each respective one of the twomultiplexers is fed by a respective control line; merging the functionsof the two multiplexers into a single multiplexer; feeding each of therespective control lines into data inputs of a control multiplexer; andusing output of the control multiplexer as a control line for the mergedmultiplexer.
 5. A programmable logic device comprising: a mergedmultiplexer capable of performing the functions of two independentmultiplexers, the two independent multiplexers receiving identical datainputs and not both being used by the programmable logic device toprovide outputs during any single clock cycle, each respective one ofthe multiplexers being fed by a respective control line, wherein: eachof the respective control lines is fed into a data input of a controlmultiplexer; and output of the control multiplexer is used as a controlline for the merged multiplexer.
 6. The device of claim 5 furthercomprising: a plurality of multiplexers that form a multiplexer cone;wherein: the two independent multiplexers being are selected from amongthe plurality of multiplexers that form the multiplexer cone.
 7. Thedevice of claim 6, wherein the multiplexer cone is characterized as aplurality of multiplexers the outputs of all but one of which only feeddata inputs of other multiplexers in the cone.
 8. A printed circuitboard on which is mounted a programmable logic device as defined inclaim
 5. 9. The printed circuit board defined in claim 8 furthercomprising: memory circuitry mounted on the printed circuit board andcoupled to the programmable logic device.
 10. The printed circuit boarddefined in claim 9 further comprising: processing circuitry mounted onthe printed circuit board and coupled to the memory circuitry.